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Ordering number : ENA0654
Monolithic Linear IC
LA75520KVA
Overview
IF Signal Processing (VIF+SIF) IC that Supports the PAL Video Standard for TV Sets and VCRs
The LA75520KVA is a fully adjustment-free VIF + SIF signal processing IC for TV sets and VTRs that supports the PAL video standard. It supports 38.0MHz, 38.9MHz, and 39.5MHz as the IF frequencies, as well as PAL sound multi-system (M/N, B/G, I and D/K), and contains an on-chip sound carrier trap. The IC employs a 4MHz frequency (which can be switched to 4.43MHz) as the reference frequency of the adjustment free circuit, and controls the VCO, AFT, and sound filter using an external input signal.
Features
* Internal VCO adjustment free circuit eliminating the need for an external VCO coil. * Internal sound carrier trap enables easy configuration of PAL sound multi-system at low cost. * Considerably reduces the number of required peripheral parts. * Use of digital AFT eliminates a problem of AFT tolerance. * Package: SSOP24 (225mil)
Functions
* VIF amplifier * Adjustment-free VCO and PLL detector circuit * Digital AFT circuit * RF AGC * Buzz canceller * EQAMP * Internal sound carrier trap * First SIF detector circuit * PLL-FM detector circuit
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
80807 MS PC 20061214-S00006 No.A0654-1/12
LA75520KVA
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC Pd max Topr Tstg Ta 70C, Mounted on a substrate.* Conditions Ratings 6 640 -20 to +70 -55 to +150 Unit V mW C C
* Mounted on a substrate : 76.1x114.3x1.6mm3, glass epoxy board.
Operating Conditions at Ta = 25C
Parameter Recommended supply voltage Operating supply voltage Symbol VCC VCC op Conditions Ratings 5.0 4.5 to 5.5 Unit V V
Electrical Characteristics at Ta = 25C, VCC = 5.0V, fp = 38.9MHz
Parameter VIF block Circuit current Max RF AGC voltage Min RF AGC voltage Input sensitivity AGC range Max allowable input Quiescent video output voltage Sync signal edge voltage Video output level Black noise threshold voltage Black noise clamp voltage Video S/N C-S best Differential gain Differential phase Quiescent AFT voltage Max AFT voltage Min AFT voltage AFT sensitivity APC pull-in range (U) APC pull-in range (L) VCO control sensitivity VIF input resistance VIF input capacity N trap1 (4.5M) N trap2 (4.8M) BG trap1 (5.5M) BG trap2 (5.85M) I trap1 (6.0M) I trap2 (6.55M) DK trap1 (6.5M) Group delay 1 NTSC (3.0M) Group delay 1-1 NTSC (3.5M) Group delay 2 BG (4M) Group delay 2-1 BG (4.4M) Group delay 3 I (4M) I4 V14H V14L Vi GR Vi max V5 V5 tip VO VBTH VBCL S/N IC-S DG DP V12 V12H V12L SF Fpu Fpl Ri Ci NT1 NT2 BT1 BT2 IT1 IT2 DT1 NGD1 NGD1-1 BGD2 BGD2-1 IGD3 38.9MHz 38.9MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz wrt 1MHz 15pin to VCC LOAD 22k/22k LOAD 22k/22k LOAD 22k/22k B/G P/S = 10dB VIN = 80dB Video out 2 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 -30 -19 -27 -20 -25 -15 -25 30 110 50 120 0 3 2.0 4 0 8.5 2.0 75 4.0 0.0 26 58 95 2.2 0.8 1.0 0.5 1.2 46 38 85 4.5 0.5 32 63 100 2.5 1.0 1.2 0.8 1.5 50 43 3 3 2.5 4.5 0.5 12.5 2.4 -2.4 6 1.0 3 -35 -24 -32 -25 -30 -20 -30 80 200 130 200 80 145 290 210 280 130 -2.0 12 1.5 6 6.5 5 3.0 5 1 16.5 2.8 1.2 1.4 1.1 1.8 95 5.0 1.0 38 mA V V dBV dB dBV V V Vp-p V V dB dB % deg V V V mV/kHz MHz MHz kHz/mV k pF dB dB dB dB dB dB dB ns ns ns ns ns Symbol Conditions No. min Ratings typ max Unit
Continued on next page.
No.A0654-2/12
LA75520KVA
Continued from preceding page. Parameter Group delay 3-1 I (4.4M) Group delay 4 DK (4M) Group delay 4-1 DK (4.4M) Video f characteristics MN1 Video f characteristics MN2 Video f characteristics MN3 Video f characteristics BG1 Video f characteristics BG2 Video f characteristics BG3 Video f characteristics I1 Video f characteristics I2 Video f characteristics I3 Video f characteristics DK1 Video f characteristics DK2 Video f characteristics DK3 Group delay 2-2 BG shift (4M) Group delay 2-3 BG shift (4.4M) 1st SIF Block SIF carrier output level 1 SIF carrier output level 2 1st SIF max input 1st SIF input resistance 1st SIF input capacity SIF Block Limiting sensitivity (SPLIT) Limiting sensitivity (INTER) FM detection output voltage AM removal ratio Distortion factor FM detection output S/N PAL/NT audio voltage gain difference PAL De-emphasis NT De-emphasis Control Block SIF system SW threshold voltage A/B 38MHz/38.9MHz threshold voltage 38.9MHz/39.5MHz threshold voltage Inter-carrier system AFT mute level/SIF trap shift threshold voltage 1 AFT mute level/SIF trap shift threshold voltage 2 AFT mute level/SIF trap shift threshold voltage 3 Others Ref clock input level Reference frequency SW threshold resistance Continued on next page. Reflev R11 4.0MHz O1 O2 83 150 90 270 95 dBV k V15th3 C7 3.7 4.0 4.3 V V15th2 C6 2.2 2.5 2.8 V V7_9th V10th1 V10th2 V13th V15th1 C1 C2 C3 C4 C5 0.7 1.0 2.2 0.7 3.7 2.5 1.0 4.0 2.8 1.3 4.3 0.3 1.3 V V V V V Vi (lim) (SP) Vi (lim) (IN) VO (FM) AMR THD S/N (FM) GD Pdeem Ndeem P = 80dB CW P = 80dB CW P = 80dB P/S f = 5.5MHz, F = 30kHz S1 S2 S3 S4 S5 S6 S7 S8 S9 55 20 29 390 50 25 35 560 60 0.3 60 6 -3 -3 0.8 30 41 730 dBV dB mVrms dB % dB dB dB dB So1 So2 Si max Ris Cis 33.4MHz 33.4MHz Vi = 1mV Vi = 10mV F1 F2 F3 F4 F5 21 21 110 43 43 120 2 3 2.4 6 86 86 mVrms mVrms dBV k pF Symbol IGD3-1 DGD4 DGD4-1 VFMN1 VFMN2 VFMN3 VFBG1 VFBG2 VFBG3 VFI1 VFI2 VFI3 VFDK1 VFDK2 VFDK3 BGD2-2 BGD2-3 wrt 1MHz wrt 1MHz wrt 1MHz M/N 1 to 2MHz M/N 2 to 3MHz M/N 3.58MHz B/G 1 to 3MHz B/G 3 to 4MHz B/G 4.43MHz I 1 to 3MHz I 3 to 4MHz I 4.43MHz D/K 1 to 3MHz D/K 3 to 4MHz D/K 4.43MHz wrt 1MHz wrt 1MHz Conditions No. min V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 80 10 30 -1.0 -1.0 -3.0 -1.0 -1.5 -2.5 -1.0 -1.0 -1.5 -1.0 -1.0 -1.5 50 110 Ratings typ 120 30 60 0.0 0.0 -1.5 0.0 0.0 -1.0 0.0 0.0 0.0 0.0 0.0 0.0 100 180 max 160 50 90 1.0 1.0 0.0 1.5 1.5 0.5 1.0 1.5 1.5 1.0 1.5 1.5 150 250 ns ns ns dB dB dB dB dB dB dB dB dB dB dB dB ns ns Unit
No.A0654-3/12
LA75520KVA
Package Dimensions
unit : mm (typ) 3287
Allowable power dissipation, Pd max - mW
1400
Pd max -- Ta
Specified board : 76.1x114.3x1.6mm3 glass epoxy When mounted on a board
6.5 24 13
1200
1000
4.4
6.4
800
0.5
600
1 0.5 (0.5) 0.22
12 0.15
400
1.5max
200 0 - 20
(1.3)
0
20
40
60
70
80
Ambient temperature, Ta - C
SANYO : SSOP24(225mil)
0.1
No.A0654-4/12
LA75520KVA
System changeover
a. SIF system SW The SIF system can be changed over by setting A (pin 7) and B (pin 9) to GND and OPEN respectively.
A GND GND OPEN OPEN B GND OPEN GND OPEN O O O BG I DK MN O FM DET LEVEL 6dB 0dB 0dB 0dB De-emphasis 75s 50s 50s 50s
Note : Circles mean that the system indicated with a circle is selected
b. IF system SW The IF frequency becomes 38.9MHz when pin 10 is open. The IF frequency becomes 38.0MHz when pin 10 is set to GND. The IF frequency becomes 39.5MHz when pin 10 is set to VCC. c. Split/inter carrier SW Inter-carrier is selected by setting the 1st SIF input (pin 13) to GND. d. Reference frequency changeover SW The reference frequency becomes 4.43MHz when pin 11 is OPEN. The reference frequency becomes 4.0MHz when 270k is connected between pin 11 and GND. e. AFT mute level, trap point shift SW By changing the pin 15 voltage, the potential and TRAP point at which AFT is muted can be set to either just or shift (about +220kHz).
Pin 15 potential VCC to 4V 4V to 2.5V 2.5V to 1V 1V to GND * VCC=5V AFT mute potential MIDDLE (VCC/2) MIDDLE (VCC/2) HI (VCC) HI (VCC) TRAP point shift Just Shift Just Shift
f. FM detector function not used To stop FM detection VCO without using the SIF circuit, short-circuit pin 1 - GND with resistance of 1k or less.
No.A0654-5/12
LA75520KVA
Pin Assignment
DE-EMPHASIS C 1 SIF AGC FILTER 2 FM PLL FILTER 3 VCC 4 VIDEO OUTPUT 5 EQ FILTER 6 SIF SYSTEM SW A 7 APC FILTER 8 SIF SYSTEM SW B 9 VIF FREQUENCY SW 10 REFERENCE CP INPUT 11 AFT OUTPUT 12 Top View 24 AUDIO OUTPUT 23 FILTER CONTROL C 22 AUDIO BIAS FILTER 21 SIF CARRIER OUTPUT 20 RF AGC VR 19 GND
LA75520KVA
18 VIF IN1 17 VIF IN2 16 VIF AGC FILTER 15 AFT MUTE LEVEL 14 RF AGC OUTPUT 13 1st SIF INPUT
Block Diagram and Sample Application
VIF/SIF INPUT SOUND CARRIER OUTPUT RF AGC OUTPUT V4 SW15 AUDIO OUTPUT SAWF(P) SAWF (S) V3 V2 V1 SW13
SW10 V3 V2 V1
VIF FREQUENCY 39.5MHz 38.9MHz 38.0MHz
0.022F
1F
1F
SW11 OPEN SHORT
REFERENCE 4.43MHz 4.0MHz
24
23
22
21
20
RF AGC
19
18
VIF AMP
17
16
15
14
13
SW13
SYSTEM SPLIT INTER
DEEMP IF AGC SPLI AMP AMP INT FM DET TRAP
TRAP
1 stSIF AMP AGC
OPEN SHORT
VIDEO DET
COM
SW15 V4
ATF MUTE LEVEL B/G TRAP SHIFT 0 MIDDLE(VCC/2) HI(VCC) +250kHz 0 +250kHz
VCO OMD PHASE CTL APC SW MODE CTRL
V3 V2
AFT
V1
Pin7 Hi Hi Lo Lo
Pin9 Hi Lo Hi Lo
SIF SYSTEM B/G I D/K M
SIF AMP AGC EQ AMP
1
0.01F 0.01F
2
330pF
3
3.3k 0.033F
4
5
6
7
8
0.47F
9
10
SW10
11
12
AFT OUTPUT
270k SW11
51
1000pF
V3 V2 V1 SYSTEM SW B VIF FREQ.
VCC(5V)
SYSTEM SW A
4.43/4MHz
VIDEO OUTPUT
PCA01178
No.A0654-6/12
LA75520KVA
Input Impedance Test Circuit (VIF and first SIF input impedance)
Impedance analyzer VIF IN 1st SIF IN
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F
0.01F 15 14
24
23
22
21
20
19
18
17
16
0.01F 13
LA75520KVA
22k 22k
1 0.01F 0.01F
2 0.01F
3
4 1k
5 0.01F
6 0.01F
7 0.01F
8 0.01F
9 0.01F
10 0.01F
11 0.01F
12
VCC 0.01F 100F
No.A0654-7/12
LA75520KVA
Pin Functions
Pin No. 1 Pin name DE-EMPHASIS C Function De-emphasis capacitor connection pin This is used to switch the equivalent resistance (5k or 7.5k) internally in the IC to select the time constant. This switching is linked to the SIF input switch. To disable de-emphasis, disconnect the capacitor. Connection of an external capacitance of 0.01F enables switching between 50 and 75s. When the FM detector circuit is not to be used, the FM VCO can be stopped by connecting it to ground with a resistor of 1k or less.
0.01F 4k
Equivalent Circuit
1
2
SIF AGC FILTER
AGC filter pin for SIF carrier 0.01F is recommended for C1.
2k
2
C1
3
FM PLL FILTER
PLL filter pin of FM detector This is used to configure an external lag lead filter. Example: Connect 330pF in parallel with the filter on the left (0.033F + 3.3k).
3
0.033F 330pF 3.3k
8k
3
4 5 6 VCC EQ OUT EQ FILTER Power supply Equalizer circuit. This circuit is used to correct the video signal frequency characteristics. Notes on equalizer amplifier design * The equalizer amplifier is designed as a voltage follower amplifier with a gain of about 0 dB. When used for frequency characteristics correction, a capacitor, inductor, and resistor must be connected in series between pin 6 and ground. R1 Equalizer amplifier gain AV = Z + 1 R1 is the IC internal resistance, and is 1k. In the application design, simply select Z to correspond to the desired characteristics. However, since the EQ amplifier gain will be maximum at the resonant point defined by Z, care is required to assure that distortion does not occur.
2k R1:1k
5
6
C L R
Z
Continued on next page.
No.A0654-8/12
LA75520KVA
Continued from preceding page. Pin No. 7 9 Pin name SIF SYSTEM SW A Function SIF system selection switch pins. Combining the
50k 1k
Equivalent Circuit
In M/N mode, the audio output level is increased by 6dB. The internal trap is also linked to these switches. The truth-values are as follows. Pin7 H H L L Pin9 H L H L MODE B/G I D/K
7
80k 1k 30k 80k 1k
9
8
APC FILTER
PLL APC filter connection pin. The APC count is switched internally in the IC. The VCO is normally controlled by route A. When unlocked and during weak field reception, the VCO is controlled by route B and the loop gain is increased. For this APC filter we recommend a resistor of 51 and capacitor of 0.47F. The buzz characteristics can be improved by connecting a capacitor of 100pF or so between pins 5 and 8.
B A from APC DET 1k
1k
10
VIF FREQUENCY SW
Switch pin for selecting the IF frequency When this pin is open, 1/2VCC exists. VCC : 39.5MHz Open : 38.9MHz GND : 38.0MHz
50k
30k
M/N
1k
50k
settings of these two pins supports four systems.
8
11k 50k
10
11
REFERENCE CP INPUT
Reference signal input pin necessary for adjusting the internal sound carrier trap, AFT, etc. Either 4.0 or 4.43 MHz can be selected. Use the configuration shown in example 1 when using 4.43MHz and configuration shown in example 2 when using 4.0MHz. Since no oscillator can be configured simply by reference signal from an external source without fail.
Example 1 Example 2
11
1000pF 1000pF
11
270k
4.43MHz
4.0MHz
200k
connecting the X'tal resonator to pin 11, input the
11
Continued on next page.
No.A0654-9/12
LA75520KVA
Continued from preceding page. Pin No. 12 Pin name AFT OUTPUT Function AFT output pin. The AFT center voltage is generated by an external bleeder resistor. The AFT gain is increased by increasing the resistance of this external bleeder resistor. For the resistor we recommend a resistance equal to or greater than 22k. For the filter C1 we recommend a capacitance of 0.1F.
500 500
Equivalent Circuit
R
12
R
C1
13
1st SIF INPUT
First SIF input pin. A DC cut capacitor must be used in the input circuit. (a) If a SAW filter is used : The first SIF sensitivity can be increased by inserting an inductor between the SAW filter and the IC to neutralize the SAW filter output capacitance and the IC input capacitance. (b) When used in an intercarrier system : Connect this pin to ground.
2k
13
VCC
14
RF AGC OUTPUT
RF AGC output pin. This output controls the tuner RF AGC. This is the open collector output and a protective 200 resistor is inserted. Determine the external bleeder resistor value in accordance with the specifications of the tuner.
200
14
15
AFT MUTE LEVEL
A switch pin for selecting the mute potential when muting is applied to the AFT due to PLL unlock, etc. At the same time, it is used to control the trap point shift of the audio trap (in the B/G mode). When the frequency characteristics of the video band are to be made as flat as possible with the split input, the trap can be shifted to the high range although the attenuation of the sound carrier will drop. Therefore, when used in combination with the SAW filter, verify that the level is high enough before use. Voltage VCC to 4V 4V to 2.5V 2.5V to 1V 1V to GND * When VCC = 5 V Continued on next page. ATF MUTE Voltage VCC/2 VCC/2 VCC VCC 0 +250kHz 0 +250kHz TRAP SHIFT
66k
15
34k
No.A0654-10/12
LA75520KVA
Continued from preceding page. Pin No. 16 Pin name IF AGC Function IF AGC filter connection pin. The signal peak-detected by the built-in AGC detector is converted to the AGC voltage at pin 16. Additionally, a second AGC filter (a lag-lead filter) used to create the dual time constants is provided internally in the IC. Use a 0.022F capacitor as the external capacitor (C1), and adjust the value according to the sag, AGC speed, and other characteristics.
1k 1k 5k
Equivalent Circuit
16
C1
17 18
VIF IN2 VIF IN1
VIF amplifier input pin The input circuit is a balanced circuit, and the input impedance is as follows:
1k 1k
R 1.0k
17 18
19 20
GND RF AGC VR RF AGC volume connection pin This pin sets the tuner RF AGC operating point. Also, the FM output and the video output can both be muted at the same time by connecting this pin to ground.
20
21 SIF CARRIER OUT First SIF output pin This is an emitter-follower output with a 200 resistor attached in series.
1k
1k
200
21
22
AUDIO BIAS FILTER
Connection pin for a filter used to hold the FM detector output DC voltage fixed. Normally, a 1F electrolytic capacitor should be used. The capacitance (CI) should be increased if the low band (around 50Hz) frequency characteristics need to be improved.
300
300 40k
40k
22
+ C1
Continued on next page.
No.A0654-11/12
LA75520KVA
Continued from preceding page. Pin No. 23 C Pin name FILTER CONTROL Function Internal filter (trap) control pin Connect a capacitor with a capacitance between 0.47 to 1F, depending on the video S/N as well as the levels of the AM and PM noise. Equivalent Circuit
23
24 AUDIO OUTPUT Sound output pin Emitter follower output
24
1k
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of August, 2007. Specifications and information herein are subject to change without notice. PS No.A0654-12/12

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